DDR3 SDRAM in electronic engineering terms stands for double-data-rate three synchronous dynamic random access memory. This random access memory interface technology is used by computer or other digital electronic devices for high bandwidth storage of working data. One of the many dynamic random access memory (DRAM) implementations DDR3 is part of the SDRAM family of technologies. The DDR3 SDRAM is quite a significant improvement over its predecessor, the DDR2 SDRAM and its primary benefit is its ability to transfer the data at almost double the rate at which DDR2 (I/O is at 8 times the data rate of the contained memory cells) does, thereby enabling a much improved and higher bus rates and peak rates then the earlier memory technologies. However there is no noticeable reduction in latency which is a feature of the DRAM array and not due to the interface. Also the DDR3 enables a maximum module size of 16 gigabytes with chip capacities of 512 megabits and 8 gigabits. A point to note is that the DDR3 is only a DRAM interface specification, whereas the actual DRAM arrays that stores the data are similar to any other type of DRAM along with similar performance.

Some of the advantages apart from the speed of data transfer are that it provides a significant reduction in power consumption of 30% as compared to DDR2 modules. Its high speed of data transfer comes from the higher bandwidth due to the 8 bit deep prefetch buffer as compared to DDR2’s 4 bit and DDR’s 2 bit prefetch buffer. Another advantage for DDR3 is the slightly improved latencies when measured in nanoseconds. It also provides higher performance at low power and thus helps maintain longer battery life in laptops. It also provides enhanced low power features. As far as some of its disadvantages are concerned starting April 2009 it costs a bit higher than the equivalent DDR2 memory. Also another expense attached with it is the new and more expensive motherboards.

The components of DDR3 include the newly introduced asynchronous RESET pin, support for system level flight time compensation, Read and Write calibration, On-die I/O calibration engine, introduction of CAS write latency also called CWL per clock bin, and an On-DIMM mirror friendly DRAM pin out. The modules include high precision calibration resistors, fly by command/control /address bus with On-DIMM termination. The drawback here is that these modules are not backward compatible in the sense that DDR3 modules do not fit into DDR2 sockets and in case you try and force them it can damage the DIMM and/or the motherboard.

DDR3 sales would in all possibility overtake the sales of DDR2 by year end or early 2010. As per IDC in early January this year the DDR3 sales would account for 29% of total DRAM units sold in this year. The successor for DDR3 likely to be named DDR4 is expected to be released by 2012 with even less power consumption of 1.2 volts as compared to the 1.5 volts of DDR3 chips and with data transfer speed in excess of 2 billion data transfers per second.

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